Table of Contents
Advertisement
IEEE-488 Reference
Standard Event Status Register — This is a latched read
only register that is used to record the occurrence of standard
events. Each used bit in the register represents a standard
event. Descriptions of these standard events are provided in
paragraph 5.10.4.
When a standard event occurs, the appropriate bit in the
Standard Event Status Register sets. For example, if you at-
tempt to read data from an empty Output Queue, a Query Er-
ror (QYE) will occur and set bit B2 of the status register. A
set bit in this register will remain set until an appropriate op-
eration is performed to clear the register. The Standard Event
Status Register can be read at any time by using the follow-
ing common query command (see paragraph 5.10.4 for de-
tails):
*ESR?
Reading this register using the *ESR? command also clears
the register. The following list summarizes all operations that
clear the Standard Event Status Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the *ESR? common command.
Standard Event Status Enable Register — This register is
programmed by the user and serves as a mask for standard
events. When a standard event is masked, the occurrence of
that event will not set the Event Summary Bit (ESB) in the
Status Byte Register. Conversely, when a standard event is
unmasked, the occurrence of that event will set the ESB bit.
A bit in the Standard Event Status Register is masked when
the corresponding bit in the Standard Event Status Enable
Register is cleared (0). When the masked bit of the Standard
Event Status Register sets, it is ANDed with he correspond-
ing cleared bit in the Standard Event Status Enable Register.
The logic "0" output of the AND gate is applied to the input
of the OR gate and thus, will not set the ESB bit in the Status
Byte Register.
A bit in the Standard Event Status Register is unmasked
when the corresponding bit in the Standard Event Status En-
able Register is set (1). When the unmasked bit of the Stan-
dard Event Status Register sets, it is ANDed with the
5-8
Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com
corresponding set bit in the Standard Event Status Enable
Register. The logic "1" output of the AND gate is applied to
the input of the OR gate and thus, sets the ESB bit in the Sta-
tus Byte Register.
The individual bits of the Standard Event Status Enable Reg-
ister can be set or cleared by using the following common
command (see paragraph 5.10.2):
*ESE <NRf>
The Standard Event Status Enable register can be read at any
time by using the following common query command (see
paragraph 5.10.3 for details):
*ESE?
Reading this register using the *ESE? command does not
clear the register. The following list summarizes all opera-
tions that will clear the Standard Event Status Enable Regis-
ter:
1. Cycling power.
2. *ESE 0
5.6.2 Operation event status
The reporting of operation events is controlled by a set of 16-
bit registers; the Operation Condition Register, the Transi-
tion Filter, the Operation Event Register, and the Operation
Event Enable Register. Figure 5-7 shows how these registers
are structured.
Notice in Figure 5-5 that bits B5 (Waiting in Trigger Layer)
and B6 (Waiting in An Arm Layer) of the Operation Condi-
tion Register are controlled by the arm register set and the
trigger set and the trigger register set (see paragraph 5.6.3
and 5.6.5 for details). Each of the bits that is used in these
registers represents an operation event. Descriptions of the
operation event bits are provided in paragraph 5.16.
The operation status registers are controlled by the :STATus
:OPERation commands in the :STATus subsystem (see para-
graph 5.16.
Advertisement
Table of Contents
