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Figure 5-23
Arm Event Enable Register
Figure 5-24
Sequence Event Enable Register
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:STATus Subsystem
Bit Position
(B15 - B2)
Event
Decimal Weighting
Value
Value : 1 = Enable Arm Event
0 = Disable (Mask) Arm Event
Event : Seq 1 = Sequence 1
Bit Position
(B15 - B3)
Event
Decimal Weighting
Value
Value : 1 = Event Bit Set
0 = Event Bit Cleared
Event : Lay1 = Layer 1
Lay2 = Layer 2
IEEE-488 Reference
B1
B0
Seq1
2
1
(2 )
0/1
B2
B1
B0
Lay2
Lay1
4
2
2
1
(2 )
(2 )
0/1
0/1
5-103
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