3-16
Operation
Event register sets
An event register set is made up of an event register and an event enable register
3-5). When an event occurs, the appropriate event register bit sets to 1. The bit remains
latched (to 1) until the register is reset. When an event register bit is set and its
corresponding enable bit is set (as programmed by the user), the output (summary) of the
register will set to 1, which in turn sets the summary bit of the status byte register.
Figure 3-5
Standard event status
*ESR?
To ESB Bit
of Status Byte
OR
Register
*ESE <NRf>
*ESE?
Decimal
Weights
S46-901-01 Rev. C / January 2006
PON
(B15 - B8)
(B7)
(B6)
(B7)
&
&
PON
(B15 - B8)
(B7)
(B6)
(B7)
128
7
(2
)
PON = Power On
CME = Command Error
EXE = Execution Error
DDE = Device-Dependent Error
QYE = Query Error
OPC = Operation Complete
S46/S46T Microwave Switch System Instruction Manual
CME
EXE
DDE
QYE
(B2) (B1)
(B5)
(B4)
(B3)
&
&
&
&
CME
EXE
DDE
QYE
(B2) (B1)
(B5)
(B4)
(B3)
32
16
8
4
5
4
3
2
(2
)
(2
)
(2
)
(2
)
& = Logical AND
OR = Logical OR
(Figure
Standard Event
OPC
Register
(B0)
&
OPC
Standard Event
Enable Register
(B0)
1
0
(2
)