Xilinx VC709 User Manual page 67

Table 1-26: Mode Switch SW11 Settings
Figure 1-28
X-Ref Target - Figure 1-28
The mode pins settings on SW11 determine if the linear BPI flash is used for configuring the FPGA.
DIP switch. SW11 also provides the upper two address bits for the linear BPI flash and can be used
to select one of multiple stored configuration bitstreams.
between the onboard nonvolatile flash devices used for configuration and the FPGA.
To obtain the fastest configuration speed, an external 80 MHz oscillator is wired to the EMCCLK
pin of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit
datapath from the linear BPI flash memory at a maximum synchronous read rate of 80 MHz.
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
Mode Pins
Configuration Mode
(M2, M1, M0)
010
101
shows mode switch SW13.
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
R396
1.21kΩ
0.1 W
1%
R397
1.21kΩ
0.1 W
1%
GND
Figure 1-28: Mode Switch
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Master BPI
JTAG
SW11
ON
10
9
8
7
6
SDA05H1SBD
R398 R400
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R399
1.21kΩ
0.1 W
1%
Figure 1-29
Configuration Options
VCC2V5
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
1
2
3
4
5
UG887_c1_27_090612
shows the connectivity
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