Xilinx VC709 User Manual page 3

Date Version
04/30/2014 1.3
12/04/2014 1.4
09/02/2015 1.4.1
03/18/2016 1.5
08/12/2016 1.5.1
03/11/2019 1.6
UG887 (v1.6) March 11, 2019
small outline dual-inline memory modules (SODIMMs) in
Revised the data rate for the
Board Features and Dual DDR3 Memory
Added MT28GU01GAAA1EGC-0SIT part number for the BPI parallel NOR flash memory
component to Table 1-1, Linear BPI Flash
Updated User SMA Clock (USER_SMA_CLOCK_P and
Jitter-Attenuated Clock, I2C
Updated Figure 1-11 to correct net names. Added I/O standard information to
Table 1-5, Table 1-6, Table 1-8,
connector information after Table
Table 1-25. Updated Table A-3
Made typographical edits.
Updated Figure 1-16. Added thickness information in
Made a typographical edit.
Added the latest version of ESD Directive in
description of Dual DDR3 Memory
changed the title of the appendix, updated the description, and removed the VC709 Board XDC
Listing. Updated Appendix F, Regulatory and Compliance
Additional Resources.
www.xilinx.com
Revision
SODIMMs.
Memory, and References. Added a note to
Bus, and Power Management. Updated part number in
Table 1-14, Table 1-19, and
1-12. Updated description for XADC_GPIO_3, 2, 1, 0 in
and added Figure A-3. Updated References.
Appendix E, Board
Electrostatic Discharge
SODIMMs. In Appendix C, Xilinx Design Constraints
Table
USER_SMA_CLOCK_N),
Figure
Table 1-4,
Table 1-20. Added PCIe® edge
Specifications.
Caution. Updated the
Information. Updated Appendix G,
VC709 Evaluation Board
VC709
1-1.
1-4.