Xilinx VC709 User Manual page 40

VC709 Evaluation Board Features
Chapter 1:
Table 1-10: PCIe Edge Connector Connections (Cont'd)
Net Name FPGA (U1) Pin
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_TX5_P
PCIE_TX5_N
PCIE_TX6_P
PCIE_TX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_PRSNT_B J49 2, 4, 6
PCIE_WAKE_B AV33
PCIE_PERST_B AV35
40
Send Feedback
PCIe Edge
Connector (P1)
Pin Name
AA2 A21 PERp1
AA1 A22 PERn1
AC2 A25 PERp2
AC1 A26 PERn2
AE2 A29 PERp3
AE1 A30 PERn3
AG2 A35 PERp4
AG1 A36 PERn4
AH4 A39 PERp5
AH3 A40 PERn5
AJ2 A43 PERp6
AJ1 A44 PERn6
AK4 A47 PERp7
AK3 A48 PERn7
AB8 A13 REFCLK+
AB7 A14 REFCLK-
A1 PRSNT#1
B11 WAKE#
A11 PERST
www.xilinx.com
Function
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
differential clock pair from
PCIe
Integrated Endpoint block
differential clock pair from
PCIe
J49 Lane Size Select jumper
Integrated Endpoint block
wake signal
Integrated Endpoint block
reset signal
FFG1761 Placement
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y16
MGT_BANK_115
MGT_BANK_115
NA
U1 FPGA Bank13 Pin AV33
U1 FPGA Bank13 Pin AV35
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019