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VC709 Evaluation Board Features
Chapter 1:
GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)
[Figure
The VC709 board includes a pair of SMA connectors for a GTH clock wired to GTH Quad bank
113. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N,
which are connected to FPGA U1 pins AK8 and AK7 respectively.
AC-coupled clock circuit.
•
•
X-Ref Target - Figure 1-10
Jitter-Attenuated Clock
[Figure
The VC709 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the board.
FPGA user logic can implement a clock recovery circuit and then output this clock to a differential
I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin AW32 and REC_CLOCK_C_N, FPGA
U1 pin AW33) for jitter attenuation. The jitter-attenuated clock (Si5324_OUT_C_P,
Si5324_OUT_C_N) is then routed as a reference clock to GTH Quad 113 inputs MGTREFCLK0P
(FPGA U1 pin AH8) and MGTREFCLK0N (FPGA U1 pin AH7). The Si5324 U24 jitter attenuator
has two LVCMOS18 connections to the XCVX690T FPGA U1.
The Silicon Labs Si5324 U24 pin 1 reset net SI5324_RST must be driven High to enable the device.
U24 pin 3 net SI5324_INT_ALM is level-shifted to 1.8V by U47 and is connected to U1 bank 13
pin AU34. U24 pin 1 net SI5324_RST is level-shifted to 1.8V by U39 and is connected to U1 bank
13 pin AT36. An active-Low input performs an external hardware reset of device. This resets all
internal logic to a known state and forces the device registers to their default value. The clock
outputs are disabled during reset. The part must be programmed after a reset or power-on to get a
clock output. The reset pin 1 has a weak internal pull-up.
32
Send Feedback
1-2, callout 8]
External user-provided GTH reference clock on SMA input connectors
1.8V differential input
J25
SMA_MGT_REFCLK_C_P
SMA
Connector
J26
GND
SMA_MGT_REFCLK_C_N
SMA
Connector
GND
Figure 1-10: GTH SMA Clock Source
1-2, callout 9]
www.xilinx.com
Figure 1-10
shows this
C25
SMA_MGT_REFCLK_P
0.01 μF 25V
X7R
C24
SMA_MGT_REFCLK_N
0.01 μF 25V
X7R
UG887_c1_10_090612
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
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