Xilinx VC709 User Manual page 29

Table 1-8
Table 1-8: Clock Connections, Source to FPGA
Clock Source Pin
U51.5
U51.4
U34.5
U34.4
J26.1
J25.1
J32.1
J31.1
U24.29
U24.28
U13.5
U13.4
U40.3
System Clock (SYSCLK_P and SYSCLK_N)
[Figure
The VC709 board has an LVDS 200 MHz oscillator (U51) soldered onto the back side of the board
and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is named
SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins H19 and G18 respectively.
•
•
•
The LVDS termination resistor R2, located within the FPGA via matrix on the bottom of the board,
is not populated. One possible I/O standard for the FPGA design clock input is:
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
lists the pin-to-pin connections from each clock source to the FPGA.
Net Name
SYSCLK_N
SYSCLK_P
USER_CLOCK_N
USER_CLOCK_P
SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_P
USER_SMA_CLOCK_N
USER_SMA_CLOCK_P
Si5324_OUT_N
Si5324_OUT_P
SYSCLK_233_N
SYSCLK_233_P
FPGA_EMCCLK
1-2, callout 5]
Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential output
NET "sysclk_p" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank 38
MRCC input
NET "sysclk_n" LOC = "G18" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R2 DNP
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Feature Descriptions
I/O Standard XCVX690T (U1) Pin
DIFF_SSTL15
DIFF_SSTL15
LVDS
LVDS
NA
NA
LVDS
LVDS
LVDS
LVDS
DIFF_SSTL15
DIFF_SSTL15
LVCMOS18
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G18
H19
AL34
AK34
AK7
AK8
AK32
AJ32
AH7
AH8
AY17
AY18
AP37
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