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Table 1-14
Table 1-14: SFP+ Module Control and Status
XCVX690T (U1) Pin
SFP+ Module 1 (P3)
Y38
AB42
W40
Y40
Y39
AB41
SFP+ Module 2 (P2)
AA39
AA42
AB38
AB39
AA40
Y42
SFP+ Module 3 (P4)
AA41
AC39
AD42
AE42
AD38
AC38
SFP+ Module 4 (P5)
AE38
AC41
AE39
AE40
AD40
AC40
Note:
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
lists the SFP+ module control and status connections to the FPGA.
Net Name
SFP1_TX_FAULT
SFP1_MOD_DETECT
SFP1_RS0
SFP1_RS1
SFP1_LOS
SFP1_TX_DISABLE
SFP2_TX_FAULT
SFP2_MOD_DETECT
SFP2_RS0
SFP2_RS1
SFP2_LOS
SFP2_TX_DISABLE
SFP3_TX_FAULT
SFP3_MOD_DETECT
SFP3_RS0
SFP3_RS1
SFP3_LOS
SFP3_TX_DISABLE
SFP4_TX_FAULT
SFP4_MOD_DETECT
SFP4_RS0
SFP4_RS1
SFP4_LOS
SFP4_TX_DISABLE
The six control/status signals to/from each SFP+ connector are routed through a level shifter.
www.xilinx.com
I/O Standard
Pin Number
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
Feature Descriptions
SFP+ Module
Pin Name
2
TX_FAULT
6
MOD_ABS
7
RS0
9
RS1
8
LOS
3
TX_DISABLE
2
TX_FAULT
6
MOD_ABS
7
RS0
9
RS1
8
LOS
3
TX_DISABLE
2
TX_FAULT
6
MOD_ABS
7
RS0
9
RS1
8
LOS
3
TX_DISABLE
2
TX_FAULT
6
MOD_ABS
7
RS0
9
RS1
8
LOS
3
TX_DISABLE
45
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