Xilinx VC709 User Manual page 28

VC709 Evaluation Board Features
Chapter 1:
Table 1-7: VC709 Board Clock Sources
Clock Name
Source
System clock
User clock
User SMA clock
(differential pair)
GTH SMA REF clock
(differential pair)
Jitter-attenuated clock
Memory clock
FPGA EMCC clock
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Clock
SiT9102 2.5V LVDS 200 MHz fixed frequency oscillator (Si Time)
U51
See System Clock (SYSCLK_P and
2
Si570 3.3V LVDS I
(Silicon Labs).
U34
See Programmable User Clock (USER_CLOCK_P and
USER_SMA_CLOCK_P (net name)
J31
See User SMA Clock (USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N (net name)
J32
See User SMA Clock (USER_SMA_CLOCK_P and
SMA_MGT_REFCLK_C_P (net name)
J25
See GTH SMA Clock (SMA_MGT_REFCLK_P and
SMA_MGT_REFCLK_C_N (net name)
J26
See GTH SMA Clock (SMA_MGT_REFCLK_P and
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs)
U24
See Jitter-Attenuated
SiT9122 2.5V LVDS 233.33
U13
See Memory Clock (SYSCLK_233_P and
SiT8103 LVCMOS single-ended, 80 MHz, fixed-frequency oscillator (Si Time). See
U40
EMCC Clock.
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Description
SYSCLK_N).
C Programmable Oscillator, ( I
Clock.
MHz fixed frequency oscillator (Si Time).
SYSCLK_233_N).
2
C address 0x5D), 156.250 MHz default
USER_CLOCK_N).
USER_SMA_CLOCK_N).
USER_SMA_CLOCK_N).
SMA_MGT_REFCLK_N).
SMA_MGT_REFCLK_N).
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
FPGA