Xilinx VC709 User Manual page 39

Table 1-10
Table 1-10: PCIe Edge Connector Connections
Net Name FPGA (U1) Pin
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_RX4_P
PCIE_RX4_N
PCIE_RX5_P
PCIE_RX5_N
PCIE_RX6_P
PCIE_RX6_N
PCIE_RX7_P
PCIE_RX7_N
PCIE_TX0_P
PCIE_TX0_N
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
lists the PCIe edge connector connections at P1.
PCIe Edge
Connector (P1)
Pin Name
Y4 B14 PETp0
Y3 B15 PETn0
AA6 B19 PETp1
AA5 B20 PETn1
AB4 B23 PETp2
AB3 B24 PETn2
AC6 B27 PETp3
AC5 B28 PETn3
AD4 B33 PETp4
AD3 B34 PETn4
AE6 B37 PETp5
AE5 B38 PETn5
AF4 B41 PETp6
AF3 B42 PETn6
AG6 B45 PETp7
AG5 B46 PETn7
W2 A16 PERp0
W1 A17 PERn0
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Function
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Feature Descriptions
FFG1761 Placement
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
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