Toshiba Satellite 1400 Series Maintenance Manual page 27

1.2 System Unit Block Diagram
Hub Interface to ICH3-M
Power Management Support
Package:
– Package options.
– TBD pin FC-BGA (37.5 x 37.5 mm).
Trident Cyber Aladdin (NAPA2T) M1644T (Satellite 1400 series)
CPU Interface
– Supports Socket 370 family processors. Host bus frequency can be 66, 100
or 133MHz.
– 64-bit data bus and 32-bit addressing.
– Optimum buffering architecture design for CPU to memory, AGP and PCI
read/write operations.
PCI Bus Controller:
– Supports synchronous / asynchronous clock mode between the processor
bus and the PCI bus.
– 32-bit Address/Data PCI bus using PCI bus driver technology.
– Supports up to 6 PCI masters excluding the CyberBlade Aladdin i1 and
PCI-to-ISA Southbridge.
– Parity protection on all PCI bus signals.
– Fully supports PCI Configuration Space Enable (CSE) protocol.
– Fully compliant with PCI Rev. 2.2
– Supports delayed transactions.
– Dynamic memory pre-fetch algorithm and programmable post write flush
algorithm.
– Data Collection/Write assembly of line bursts.
– Supports concurrent PCI bus burst transfer at zero wait-status.
– 133MB/sec at streaming for PCI bus to DRAM access with minimum
latency.
Memory Controller:
– Supports SDR at 66, 100 or 133MHz.
– Supports DDR up to 266MHz.
– Supports symmetrical and asymmetrical SDR/DDR addressing.
– Supports 4, 16, 64, 128, 256, 512-Mbit DRAMs.
– Maximum memory size: 3.0GB
– Supports memory shadowing.
– CAS before RAS and self refresh for SDRAM.
– Pipelined SDRAM / DDR cycle control with hidden pre-charge.
– Dynamic switching CKE algorithm.
– Supports LVTTL / SSTL2 signal level.
Satellite 1400/2400 Series Maintenance Manual (960-364/365)
1 Hardware Overview
1-13