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TOSHIBA
12.5.3 Operation at the time of receiving (8 and 9 bit length multi-controller system;
RWUB = 1 when standing by for ID receiving)
1
7
8
9
1 0 1 1
S I O C L K
b i t 0
S I N
d a t a
S I N T R E Q *
S I N T R E Q *
12.5.4 Operation at the time of receiving (8 and 9 bit length multi-controller system;
RWUB = 0 when standing by for data receiving)
1
7
8
9
1 0 1 1
S I O C L K
b i t 0
S I N
d a t a
S I N T R E Q *
S I N T R E Q *
1 6
1
7
8
b i t 7
V a l i d b i t 0
W r i t e t o L i n e S t a t u s R e g . < U O E R > = 1
Fig. 12-19
Timing of Receiving (2)
1 6
1
7
8
b i t 7
V a l i d b i t 0
W r i t e t o L i n e S t a t u s R e g . < U O E R > = 1
Fig. 12-20
Timing of Receiving (3)
192
TMPR3904F Rev. 2.0
9
1 0 1 1
1 6
1
7
8
9
1 0 1 1
W a k e U p b i t = 1
V a l i d b i t 7
O v e r R u n E r r o r
W r i t e t o L i n e S t a t u s R e g . < U F E R > = 1
9
1 0 1 1
1 6
1
7
8
9
1 0 1 1
W a k e U p b i t = 0
V a l i d b i t 7
O v e r R u n E r r o r
W r i t e t o L i n e S t a t u s R e g . < U F E R > = 1
1 6
1
7
8
9
1 0 1 1
1 6
S t o p b i t
1 6
1
7
8
9
1 0 1 1
1 6
S t o p b i t
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