Toshiba TX39 Series User Manual page 185

32bit risc microprocessor
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TOSHIBA
Receive
16
RDIE
data DMA
/Interrupt
enable
Receive DMA/Interrupt Enable
When in interrupt mode (SDMAE = 0)
Valid data read request interrupt enable for
receive FIFO. Asserts the SINTREQ* signal
when there is valid data in the receive FIFO.
0:
1:
When in DMA mode (SDMAE = 1)
Read DMA request enable. Generates a read
request when the number of valid data in
the receive FIFO reaches the DMA request
trigger level.
0: Asserts the SINTREQ* signal.
1: Asserts the SDMAREQ* signal.
Fig. 12-7
DMA/Interrupt Control Register (2/2)
TMPR3904F Rev. 2.0
Disable
Enable
177

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