Interrupts - Toshiba TX39 Series User Manual

TOSHIBA
7.6

Interrupts

In the TX3904, there are eight interrupt signals (INT[7:0]) and one non-
maskable interrupt signal (NMI*).
7.6.1 INT[7:0]
The INT[7:0] is a signal to request for an interrupt of the TX3904. It is used
when the external circuit requests an interrupt. The active status of INT[7:0]
is set up in the CConR of the EBIF. There are four kinds in the active status--
the rising edge, the falling edge, the low level, and the high level.
The interrupt request by the INT[7:0] signal is arbitrated in the IRC and
informed to the TX39 Processor Core.
Processor Core, an interrupt exception occurs. The priority (interrupt level) of
the INT[7:1] interrupt can be set up in the register of the IRC.
requests by INT[0] shall be informed to the TX39 Processor Core without going
via the IRC.
When the active status of the INT[7:0] is set up at the low level or the high
level, the interrupt request must be cleared at the origin of the interrupt
request. When the active status is set up at the rising edge or the falling edge,
clear the interrupt request in the EIClr field of the CConR.
7.6.2 NMI*
The NMI* is a non-maskable interrupt request signal. This interrupt cannot be
masked. When the NMI* is asserted, the TX39 Processor Core generates a
non-maskable interrupt exception.
When the TX3904 built-in timer is operating as a watchdog timer and when
the WR bit of the CConR is 0, a non-maskable interrupt is generated when a
watchdog timer interrupt occurs.
7.7 Reset
By keeping the RESET* signal at low successively for 12 SYSCLK or more, the
TX3904 shall be initialized. All the values in the TX3904 internal registers
become the initial values.
exception.
When the TX3904 built-in timer is operating as a watchdog timer and when
the WR bit of the CConR is 1, the TX3904 shall be reset when a watchdog
timer interrupt occurs.
TMPR3904F Rev. 2.0
When it is informed to the TX39
The TX39 Processor Core generates a reset
50
Interrupt