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TOSHIBA
I/O device to Memory
Fig. 9-26 shows the timing of an I/O device to memory transfer when the data transfer unit is set
at 32 bits and the device port size at 32 bits (half speed bus mode). This figure illustrates when
2 wait cycles are set to the channel status register BSW field.
S Y S C L K
G C L K
A[31:1]
B E [3:0]*
B S T A R T *
L A S T *
R / W *
A C K *
R A S *
C A S *
W E *
D [31:0]
D A C K n *
Fig. 10-26
TMPR3904F Rev. 2.0
2 w a i t s
R O W
Single Address Mode (I/O Device → Memory)
26
157
C O L
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