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10.5.3 Input of DONE* signal
When the DIEn bit in the CCRn is set to 1, the DMAC ends the data transfer if the DONE*
signal is asserted during a data transfer.
The timing to acknowledge the DONE* signal is at the rising of the GCLK recognizing the last
internal acknowledge signal in the transfer unit. In addition to the ACK* input from outside,
acknowledge signals that are generated in the internal memory controllers (RAMC and ROMC)
and that are generated in the EBIF at the SCS accesses are also subject to this.
The timing where the DONE* signal becomes valid is shown in Fig. 9-28 that presents an
example of a memory to I/O device transfer (dual address mode) when the data transfer unit is
set at 32 bits and the device port size at 16 bits.
In a normal completion by the DONE* signal, the transfer address to be output in the next bus
operation is stored in the SARn and DARn; and the number of residual transfer bytes is stored in
the BCRn.
S Y S C L K
A[31:1]
R O W
B E [3:0]*
B S T A R T *
L A S T *
R /W*
A C K *
R A S *
C A S *
W E *
D [31:0]
D A C K n *
Fig.10-28
C O L
Transfer Completion by DONE* Signal
26
159
TMPR3904F Rev. 2.0
D e s t . A d d r .
D e s t . A d d r .
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