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bus ownership requests, the SREQ has a higher priority than the GREQ. Therefore, the priority
between the two DMAC modules depends on the daisy-chain connection when the bus
ownership request mode is the same, and it depends on the bus ownership request mode when
the kinds of the bus ownership differ.
10.2.2 DMAC internal blocks
The following Figure 10-2 shows the internal blocks of DMAC0.
Channel 1
Channel 0
31
Source Address Register
Destination Address Register
Byte Count Register
Next Byte Count Register
Channel Control Register
Channel Status Register
DMA Control Register
Data Holding Register
10.2.3 Priority between modules
In the priority between the modules, there are the priority by the daisy-chain and the priority by
the difference in the kinds of bus ownership.
(1) Priority by daisy-chain
TMPR3904F Rev. 2.0
Fig. 10-2
DMAC Internal Blocks
26
118
0
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