Channel Control Register (Ccrn) - Toshiba TX39 Series User Manual

TOSHIBA

10.3.2 Channel control register (CCRn)

3 1 3 0
Str 0
W
1 5 1 4 1 3 1 2
SAM ExR PosE Lev
R/W R/W R/W R/W R/W R/W R/W
0 0 0 0
Mnemonic Name of Field
Bit
31 Str Channel start
24 Stop Channel stop
23 NIEn Normal
completion
interrupt
enable
22 AbEn Abnormal
completion
interrupt
enable
Fig. 10-4
2 5 2 4 2 3
Stop NIEn
W R/W R/W R/W
1
1 1 1 0 9 8 7
SReq RelEn SIO SAC
R/W
0 0 0 00
Start
Starts the channel operation. By setting up this bit to 1,
the channel becomes the wait status and starts a data
transfer in response to a transfer request.
"1" is only valid to write in to the Str bit and the writing-in
of "0" is ignored. When read out, it is always "0."
1: Starts the channel operation.
Stop
Completes the channel operation to change the channel to
the halt status. The SARn and the DARn maintain the
address following the address with which the last transfer
was made. The BCRn maintains the rest of the number of
transfer bytes.
When the channel is not in the wait status, writing-ins are
ignored.
"1" is only valid to write in to the Stop bit and the writing-
in of "0" is ignored. When read out, it is always "0." Do
not set this bit "0" when the channel is not in the wait
satate.
When the Str bit and the Stop bit are simultaneously set up
to 1, the channel becomes the wait status.
1: Competes the channel operation.
Normal Completion Interrupt Enable
1: Grants a normal completion interrupt
0: Inhibits a normal completion interrupt
Abnormal Completion Interrupt Enable
1: Grants an abnormal completion interrupt
0: Inhibits an abnormal completion interrupt
Channel Control Registers (CCRn) (1/4)
26 122
TMPR3904F Rev. 2.0
2 2 2 1 2 0 1 9 1 8
AbIEn CIEn 0 DIEn DOEn
R/W R/W
1 1 0 0
6 5 4 3 2
DIO DAC TrSiz
R/W R/W
0 00 00
Description
1 7 1 6
Big
Cont
R/W R/W : Type
1 0 : Initial
Value
1 0
DPS
R/W : Type
00 : Initial
Value