Functions - Toshiba TX39 Series User Manual

TOSHIBA
10.4

Functions

This section explains the functions of DMAC0. DMAC1 has the same functions as
DMAC0.
10.4.1 Overview
The DMAC is a 32-bit DMA controller that can transfer data inside the system using the TX39
Processor Core at a high speed without the TX39 Processor Core.
(1) Source and destination
The DMAC conducts the data transfer between memories or between a memory and an I/O
device. The device at the data transfer origin is called a source device and the device at the data
transfer destination is called a destination device. Memories and I/O devices can be designated
as a source device or a destination device. The DMAC transfers from a memory to an I/O
device, from an I/O device to a memory, and from a memory to another memory; and it cannot
transfer from an I/O device to another I/O device.
The difference between a memory and an I/O device is the access method to the device. When
the DMAC accesses an I/O device, it asserts the DACKn signal. There is only one DACKn
signal in one channel so that there is only one I/O device that can be used when transferring.
Therefore, the transfer between I/O devices cannot be done.
Channel 1 (DMAC0) and Channel 2 (DMAC1) can select the TX3904 built-in serial I/O as the
I/O device. This selection of the serial I/O is conducted in the CConR of the EBIF.
(2) Transfer of bus ownership (Bus arbitration)
By a transfer request from inside or outside the DMAC, the DMAC requests of the TX39
Processor Core for the bus ownership. When a responding signal comes from the TX39
Processor Core, the DMAC is granted the bus ownership to execute the bus cycles of data
transfer.
In the bus ownership request of the DMAC, there are modes that requests/does not request for
snooping of the TX39 Processor Core built-in cache. The selection of the mode is set up in the
register of each channel.
The TX39 Processor Core sometimes requests the release of the bus ownership. Whether or not
to respond to this request is set up in the register of each channel.
When the transfer request is no longer there, the DMAC releases the bus ownership.
(3) Transfer request mode
In the transfer requests of the DMAC, there are an internal request mode and an external request
mode.
The internal request mode is a mode that generates transfer requests inside the DMAC. When
the start bit of the DMAC built-in register (Str bit of the channel control register) is set to 1, a
transfer request is generated and the DMAC starts a transfer operation.
The external request mode is a mode that generates transfer requests by the input of the transfer
request signal (DREQn) that the I/O device outputs. There are a level mode that generates
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