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TOSHIBA
12.4.5 Receiver Controller
For the receive control, the start bit is detected by the majority logic to start a data receiving
operation. Data receiving is conducted also by the majority logic. The start bit and the
receiving of the data 1 bit are sampled at SIOCLK 16 clocks. The majority logic is implemented
based on the three results of the 7th, 8th, and 9th clocks. (The data that are the same for two or
more of the three results are chosen.)
When a parity bit is attached to a 7-bit length, the parity is shifted in to the 8th bit of the receive
shift register to be stored in the highest-order bit of the receive read buffer.
When a parity bit is attached to a 8-bit length, the parity is stored in the RWUB of the line
control register.
12.4.6 Receiver shift register
This is a 8-bit shift register. It shifts in such that the first data bit that was received is bit0 (the
lowest-order bit).
12.4.7 Receiver read buffer
This is a buffer placed between the receive shift register and the receive FIFO buffer. After
receiving a data frame, the data are stored in this buffer and a parity check is conducted.
12.4.8 Transmitter controller
When the transfer shift register has taken out all of the previous data, one data frame is taken
from the transfer FIFO buffer to the transfer shift register. 1 bit is sent out every SIOCLK 16
clocks.
12.4.9 Transmitter shift register
This is a 8-bit shift register. It shifts out from the lowest order-bit in due order to transfer data.
12.4.10 Host I/F
The sending data are written into the transfer FIFO buffer by the interrupt by the sending data
empty or the DMA transfer. The writing-in by the interrupt is conducted by the byte by the
CPU. Every time the read pointer of the transfer FIFO buffer changes, an interrupt is generated
to request the CPU for sending data. In the writing-in to the transfer FIFO buffer by the DMA
transfer, when sending data of 4 bytes or 8 bytes are sent to the transfer shift register (when the
read pointer (0-7) becomes 4 and 0), a DMA request is generated and the data for sending are
taken in from the memory.
The reading-out from the receive FIFO buffer is conducted by the interrupt process or the DMA
transfer. Every time 1-byte receiving data are written in to the receive FIFO buffer (i.e., every
time the write pointer of the receive FIFO buffer moves), an interrupt is generated and the CPU
reads out the data.
In the interrupt mode, the FIFO functions as a simple one stage buffer and makes up a double-
buffer with a read buffer.
TMPR3904F Rev. 2.0
187
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