Timing Explanations - Toshiba TX39 Series User Manual

TOSHIBA
12.5

Timing Explanations

12.5.1 Operation at the time of receiving (7 and 8 bit data length)
1 0 1 1
1 7 8 9
S I O C L K
b i t 0
S I N
d a t a
S I N T R E Q *
S I N T R E Q *
12.5.2 Timing of SDMAREQ*/SMAACK* at the time of DMA I/F (at DMA level 4)
1 1 6 1 1 6 1 1 6
S I O C L K
S t a r t S t o p S t a r t
S I N
D a t a B y t e 0 D a t a B y t e 1
S t o r e T o
R C V . F I F O
S D M A R E Q *
S D A C K *
After having acknowledged the first SDMAACK* assertion, SDMAREQ* is deasserted. The
SDMAACK* is sampled by the IMCLK.
1 6 7 8
b i t 7
V a l i d b i t 0
W r i t e t o L i n e S t a t u s R e g . < U O E R > = 1
W r i t e t o L i n e S t a t u s R e g . < U P E R > = 1
Fig. 12-17 Timing of Receiving (1)
1 1 6 1 1 6 1 1 6 1 1 6
S t o p S t a r t S t o p S t a r t
D a t a B y t e 2 D a t a B y t e 3
Fig. 12-18 SDMAREQ* and SDMAACK*
191
TMPR3904F Rev. 2.0
1 0 1 1 1 0 1 1
9 1 6 1 7 8 9
P a r i t y b i t
V a l i d b i t 7
O v e r R u n E r r o r
I f P a r i t y E r r o r O c c u r
W r i t e t o L i n e S t a t u s R e g . < U F E R > = 1
1 1 6 1 1 6 1 1 6 1 1 6 1
S t o p S t a r t S t o p S t a r t
D a t a B y t e 4 D a t a B y t e 5
1 0 1 1
1 6 1 7 8 9
S t o p b i t
1 6 1 1 6 1 1 6 1 1 6 1
S t o p S t a r t S t o p S t a r t S t o p
D a t a B y t e 7
1 6
1 6