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6
CLOCKS
6.1 Clock Generator
The TX3904 has a built-in x4 frequency PLL clock generator. Please
connect a crystal oscillator with a frequency of a quarter of the internal
system clock (frequency of the TX39 Processor Core's input clock).
6.2 Operation Modes of TX3904
The following describes the operation modes by the TX3904 clock
control. The TX3904 has the normal, doze, halt, and RF modes.
6.2.1
Normal mode
Both the TX39 Processor Core and the peripheral mega cells operate at
the maximum frequencies.
Blocks that operate at the same frequency as the TX39 Processor Core:
DRAMC, ROMC, DMAC, IRC
Blocks that operate at the frequency that is a half of the TX39
Processor
Core:
TMR, SIO, PIO
6.2.2 Halt mode
The halt mode is a mode to lower the power consumption by halting
operations by halting the clocks inside the TX39 Processor Core.
By setting the halt bit of the Config register of the TX39 Processor Core,
it shifts to the halt mode.
When having entered into the halt mode, the TX39 mega cell core halts
the operation while maintaining the pipeline status. Bus release
requests from GREQ* and HPGREQ* can be replied to; but those from
the SREQ* and HPSREQ* are not replied to. The write buffer does not
halt: Therefore, when there are remaining data in the write buffer in the
halt mode, the write operation continues until the buffer becomes
empty. The SYSCLK does not halt.
The halt mode is released when the halt bit is cleared to 0 by asserting
the interrupts by on-chip peripherals (internal interrupt), INT[7:0], NMI*,
or RESET* signal. When the TX3904 is recovered from halt mode by the
above causes, the corresponding exception handler is executed.
The peripheral blocks halt partial functions by halting the clocks.
Halt mode is not usable in half speed bus mode.
Users Manual
27
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