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TOSHIBA
7.1.3
Burst read operation
The burst read operation is a bus operation to conduct refills of multiple words
of the cache at a high speed. If instructions and data to be read in by the
cache are in the memory that is managed by the TX3904 built-in memory
controller, it is a operation to be discussed in the chapters of memory
controllers ("DRAM Controller" and "ROM Controller").
The following diagram shows the timing of the burst read operation without a
wait cycle (of no wait). It is the case where the cache refill size is 4 words.
T 1
T 2
S Y S C L K
A[31:1]
B E [3:0]*
B S T A R T *
L A S T *
R /W*
A C K *
B U S E R R *
D[31:0]
S C S [3:0]*
T1 Outputs the value valid to A[31:1]. The BE[3:0]* is always low. Asserts
BSTART*.
Does not assert LAST*.
LAST* is the difference from the single read operation. Asserts the SCS[3:0]*
when the address is in the SCSn area. The R/W* becomes high because it is a
read operation.
T2 Deasserts the BSTART*.
T3 Reads in data at the timing of T3 because the ACK* is low.
T4 Reads in the first datum from D[31:0]. Reads in the datum at the timing of
T4 because the ACK* is low. Increments the value of A[31:1].
T5
Reads in the second datum from D[31:0].
timing of T5 because the ACK* is low. Increments the value of A[31:1]. Also,
asserts LAST*.
T6 Reads in the third datum from D[31:0]. Reads in the datum at the timing
of T6 because the ACK* is low. Increments the value of A[31:1]. Deasserts the
LAST*.
T7
Reads
T 3
T 4
T 5
T 6
T 7
This point that it
in
the
fourth
37
TMPR3904F Rev. 2.0
does not assert the
Reads in the datum at the
(last)
datum
from
D[31:0].
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