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TOSHIBA
TMPR3904F Rev. 2.0
DMAC0 and DMAC1 are daisy-chain connected. When DMAC0 and DMAC1 are both using
the snoop function or are both not using it, the priority is determined by the daisy-chain
connection; and DMAC0 has a higher priority than DMAC1.
When DMAC0 and DMAC1 simultaneously request of the TX39 Processor Core for the bus
ownership, DMAC0 is granted the bus ownership to start a transfer operation. DMAC1 cannot
start a transfer until DMAC0 releases the bus ownership.
Even if DMAC0 requests the bus ownership when DMAC1 has the bus ownership, the bus
ownership shall not be transferred to DMAC0 immediately. DMAC0 is made to wait until
DMAC1 releases the bus ownership.
(2) Priority by bus ownership request modes
When the bus ownership requests are different; namely, when one DMAC is using the SREQ
and the other DMAC the GREQ, the DMAC using SREQ has a higher priority.
When the DMAC using SREQ and the DMAC using GREQ simultaneously request the bus
ownership, the DMAC using SREQ obtains the bus ownership.
If the DMAC using SREQ requests the bus ownership while the DMAC using GREQ is
transferring data, the bus arbiter in the TX39 processor core requests the bus ownership at a
break of the data transfer. If the DMAC using GREQ answers to the request from the bus
arbiter, the bus ownership is transferred to the DMAC using SREQ. However, if the RelEn is
cleared to 0 in the CCRn of the DMAC using GREQ (if the bus ownership release request is not
answered), the DMAC using GREQ does not release the bus ownership and continues the data
transfer.
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