Line Status Register (Slsrn) - Toshiba TX39 Series User Manual

TOSHIBA

12.3.2 Line status register (SLSRn)

The status information about the serial data sending/receiving is given to the line status register.
3 1
1 5
Bit Mnemonic
19 UFER
18 UPER
17 UOER
0
0
Name of
Field
UART Frame Error
Frame error
Shall be set when the Stop bit is not detected. It shall
be cleared by writing "0."
invalid.
1: Frame error occurred.
UART Parity Error
Parity error
Shall be set when the UPEN of the line control register
is 1 and when an error is detected in the receiving data
in the parity bit that was added to the receiving data. It
shall be cleared by writing "0." The writing of "1" is
invalid.
1: Parity error occurred.
Overrun error UART Overrun Error
Shall be set when the overrun error occurs. It shall be
cleared by writing "0." The writing of "1" is invalid.
1: Over run error occurred.
Fig. 12-5 Line Status Register
175
TMPR3904F Rev. 2.0
2 0 1 9 1 8
UFER UPER UOER
R R
0 0
Description
The writing of "1" is
1 7 1 6
0
R : Type
0 : Initial
Value
0
: Type
: Initial
Value