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TOSHIBA
Reception
RDIS
16
data full
Receive DMA/Interrupt Status
When in the Interrupt mode (SDMAE=0)
Set to "1" when there is valid data in the
receive FIFO. This bit is cleared when a "0"
is written to it. Also, when the RDIE bit of
the DMA/Interrupt control register is set to
"1," the SINTREQ* signal is negated
simultaneous with the clearing of this bit.
When in the DMA mode (SDMAE=1)
Set to "1" when the number of valid data in
the receive FIFO reaches the DMA request
trigger level. When the RDIE bit of the
DMA/Interrupt control register is set to "1,"
RDIS is cleared and the SDMAREQ* signal is
negated when the SDMAACK* signal is
asserted. When RDIE is set to "0," the
SINTREQ* signal is negated when a "0" is
written to RDIS.
Fig. 12-9
DMA/Interrupt Status Register (2/2)
179
TMPR3904F Rev. 2.0
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