Channel Control Register 0 - Toshiba TX39 Series User Manual

TOSHIBA
9.3.1

Channel control register 0

3 1
1 5 1 4 1 3 1 2
RPS0 RPWT0
0
R/W R/W
00 11
Bit Mnemonic
31:20 RBA0 ROM channel 0
base address
14:13 RPS0 ROM channel 0
page mode
ROM page size
12:11 RPWT0 ROM channel 0
page mode wait
time
10:8 RWT0 ROM channel 0
normal mode
wait time
RBA0
R/W
0x1fc
1 1 1 0 8 7
RWT0
R/W
110
Name of Field
ROM Control Base Address on Channel 0
Designates the base address of Channel 0 using
physical address.
ROM Control Page Mode ROM Page Size
Designates the page size when the page mode Mask
ROM is used for Channel 0.
00: 4-word
01: 8-word
1*: Reserved
ROM Control Page Read Mode Wait Time on
Channel 0
Designates the number of wait cycles during the
page read when the page read Mask ROM is used
for Channel 0.
00: 0 wait
01: 1 wait
10: 2 waits
11: 3 waits
ROM Control Wait Time on Channel 0
Designates the number of wait cycles in the single
operation of Channel 0 and in the burst operation
with the Mask ROM that does not support the page
mode.
000: 0 wait
001: 1 wait
010: 2 waits
011: 3 waits
Fig. 9-3 ROM Channel 0 Control Register (1/2)
TMPR3904F Rev. 2.0
2 0 1 9
6 4 3
0 RCS0 0
R/W
101
Description
100: 4 waits
101: 5 waits
110: 6 waits
111: Reserved
88
1 6
0
: Type
: Initial
Value
2 1 0
1 RIM0 RPM0
6BUS0
R/W R/W R/W : Type
- 0 0 : Initial
Value