Transmit Halt Timing By Cts - Toshiba TX39 Series User Manual

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12.5.7 Transmit halt timing by CTS*

1 6
S I O C L K
C T S *
S h i f t - O u t
T i m i n g
S O U T S t o p B i t
T R A N S . F I F O t o
T r a n s . S h i f t R e g .
T r a n s m i t h a l t
When the CTS* has become high while sending data, that transfer is done till the data byte, and
after the transfer completion, the sending is halted. However, the next data are transferred from
the FIFO to the transfer shift register.
The CTS* becomes low to resume the sending at the first shift-out start timing.
In a transfer operation, if the host I/F is the DMA mode and if the HSE of the control register is
1, the RTS* becomes high at the same timing as the SDMAREQ* assertion and it becomes low
at the same timing as the SDMAREQ* negation.
In the interrupt mode, the RTS* becomes high at the SINTREQ* assertion and it becomes low at
the SINTREQ* negation.
1 1 6 1
S t a r t B i t
T r a n s m i t s t a r t
Fig. 12-23 Timing of CTS*
194
TMPR3904F Rev. 2.0
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b i t 0 b i t n