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TOSHIBA
TMPR3904F Rev. 2.0
transfer requests by the level detection of the DREQn signal and a edge mode that generates
transfer requests by the edge detection of the DREQn signal.
(4) Address modes
There are two address modes--a single address mode and a dual address mode.
The single address mode conducts the data transfer between a memory and an I/O device. The
memory is accessed by the address that the DMAC outputs and the I/O device is accessed
through the DACKn signal. This mode conducts reading from the source device and writing
into the destination device in one bus operation.
The dual address mode conducts the data transfer between memories or between a memory and
an I/O device. The addresses of the source device and the destination device are output by the
DMAC. When accessing the I/O device, the DMAC asserts the DACKn signal. This mode
implements the two bus operations--the read operation and the write operation. The transfer
data that were read out from the source device is temporarily taken in to the data holding register
(DHR) inside the DMAC and then is written into the destination device.
(5) Next transfer address can be set up (Continue mode)
In the single address mode, the next transfer starting address can be set up in the register in
advance (the continue mode). When the previous transfer has completed normally, the channel
being operated in the continue mode starts another data transfer, regarding the next transfer
address set up in the register as the transfer address of the new memory.
(6) Channel operations
DMAC0 has two channels (Channel 0 and Channel 1). The channel is turned on by setting the
start (Str) bit of the channel control register (CCRn) to 1; and it shall be in the wait status.
If a transfer request occurs when the channel is in the wait status, the DMAC is granted the bus
ownership to conduct the data transfer. When the transfer request is no longer there, the DMAC
releases the bus ownership to become the wait status. When the transfer completes, the channel
becomes the halt status. In the transfer completion, there are a normal completion and an
abnormal completion by causes such as an error occurrence. At the completion of a transfer, an
interrupt signal can be generated.
The following Figure 10-10 shows the outline of the status changes of the channel operations.
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