Bus Operations - Toshiba TX39 Series User Manual

TOSHIBA

BUS OPERATIONS

7
This chapter explains the bus operations of the TX3904: Operations for which
the TX3904 built-in memory controllers are not used.
7.1 Basic Bus Operations
There are three kinds in the TX3904 bus operations--the single read operation,
the burst read operation, and the single write operation.
7.1.1 System chip select
In the TX3904, there are four system chip select signals (SCS[3:0]*). These
signals are a low-active select signal made by decoding the high-order bit of
the address that the TX39 Processor Core or the built-in DMAC outputs. The
SCS[3:0]* is set up in three registers of the EBIF.
0xFFFF_E018
0xFFFF_E014
0xFFFF_E010
Table 7-1 Register Map for System Chip Select
Address Module
EBIF
EBIF
EBIF
31
TMPR3904F Rev. 2.0
Register
SCS Wait Register
SCS Mask Register
SCS Address
Register