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TOSHIBA
In the case of a burst read operation also, wait cycles can be entered by not
asserting the ACK* signal.
The following diagram shows the operation in the case where a wait cycle is
entered while the first and third data are being read.
number of waits cannot be changed at each datum.
T 1
T 2
S Y S C L K
A[31:1]
B E [3:0]*
B S T A R T *
L A S T *
R /W*
A C K *
B U S E R R *
D[31:0]
S C S [3:0]*
T 3
T 4
T 5
T 6
T 7
w a i t
w a i t
38
TMPR3904F Rev. 2.0
If SCS is used, the
T 8
T 9
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