SMART Embedded Computing MVME2502 Installation And Use Manual page 78

Functional Description
Table 4-2
Functional Signal
Name
LVDD_VSEL
BVD_VSEL[0:1]
CVDD_VSEL[0:1]
LA[20:22]
UART_SOUT[0]
TRIG_OUT
MSRCID[1] MSRCID[4]
DMA1_DDONE_B[0]
TSEC2_TXD1
TSEC2_TXD5
TSEC1_TXD[6:4]
TSEC1_TX_ER
For the following options, no strapping options provided. They are only listed for reference.
LGPL1
TSEC_1588_ALARM_
OUT2
TSEC_1588_ALARM_
OUT1
LWE1/LBS1 LA[18:19]
TSEC2_TXD[4:2]
LAD[0:15]
LGPL0
78
P2020 Strapping Options (continued)
Reset
Configuration
Name
cfg_en_use[0:7]
cfg_dram_type
cfg_sdhc_cd_pol_sel Yes
cfg_rom_loc[0:3]
cfg_sgmii2
cfg_sgmii3
cfg_srds_refclk
cfg_host_agt[0:2]
cfg_device_ID[7:5]
cfg_gpinput[0:15]
cfg_rio_sys_size
Config
Default
Resistor Description
Value
Options
eTSEC, ethernet management, 1588
Yes 1
interfaces = 2.5V
Local bus and GPIO[8:15] interfaces
Yes 11
= 3.3V
Yes 00 USB, eSDHC, SPI interface = 3.3V
Yes 11111111 default
DDR3 SDRAM selected 1.5V
Yes 1
(default)
1 SDHC polarity detect = not inverted
Yes 0110 Location of boot ROM = SPI FLASH
eTSEC2 interface operates in
No 1
parallel interface mode (default)
eTSEC3 interface operates in
No 1
parallel interface mode (default)
100MHz SERDES ref clock for PCIE
No 1
(default)
Processor acts as the host root
No 111
complex for all PCIE busses (default)
Rapid IO interface not used =>
No 111
default values used
No default value. Input pins do not
No
have internal pull-up resistors
Rapid IO interface not used =>
No 1
default values used
MVME2502 Installation and Use (6806800R96G)
Functional Description