SMART Embedded Computing MVME2502 Installation And Use Manual page 126

Programming Model
Table 7-1
CONFIG
Boot
6
Sequence
Memory
7 Debug
Config
DDR Debug
8
Config
ELBCECC
9 Enable
Config
Platform
10
Speed
CORE 0
11
Speed
12
CORE 1
13
Speed
14
DDR
15 Controller
Speed
126
POR Configuration Settings (continued)
CONFIG PINS
LGPL3/LFWP,
LGPL5
DMA2_DACK0
DMA2_DDONE0
MSRCID0
LA23
LA24
LA26
LA26
CONFIG SELECTION
CFG_BOOT_SEQ[1:0]
11 = BOOT SEQUENCE
DISABLED
Debug information
from the DDR SDRAM
1 controller is driven on
the MSPCID and
MDVAL signs (default)
Debug information is
not driven on ECC
1 pins. ECC function in
their normal mode
(default).
Default operation:
0 eLBC ECC checking is
disabled
CFG_PLAT_SPEED:1
1 =CCB CLOCK > = 333
MHz
CFG_CORE0_SPEED
1 :1=CORE FREQ>=
1000 MHz
CFG_CORE0_SPEED
0 :0=CORE
FREQ<=1000 MHz
CFG_CORE1_SPEED
1 :1=CORE
FREQ>=1000 MHz
CFG_CORE1_SPEED
0 :0=CORE
FREQ<=1000 MHz
CFG_DDR_SPEED:1=
1 DDR FREQ>= 500
MHz
MVME2502 Installation and Use (6806800R96G)
Programming Model
REMARKS
For 1200MHz board
configuration
For 800MHz board
configuration
For 1200MHz board
configuration
For 800MHz board
configuration