SMART Embedded Computing MVME2502 Installation And Use Manual page 77

Table 4-2
Functional Signal
Name
DMA2_DACK0
DMA2_DDONE0
EC_MDC
TSEC1_TXD[0,7]
TSEC2_TXD[0,7]
UART_RTS0,UART_R
TS1
TSEC1_TXD[3:1]
TSEC2_TX_ERR
MSRCID0
LA28
LA23
LA24
LA25
LA26
MVME2502 Installation and Use (6806800R96G)
P2020 Strapping Options (continued)
Reset
Configuration
Name
cfg_mem_debug
cfg_ddr_debug
cfg_tsec_reduce
cfg_tsec1_prctcl[0:1]
cfg_tsec2_prctcl[0:1]
cfg_tsec3_prctcl[0:1]
cfg_io_ports[0:3]
cfg_elbc_ecc
cfg_sys_speed
cfg_plat_speed
cfg_core0_speed
cfg_core1_speed
cfg_ddr_speed
Functional Description
Config
Default
Resistor Description
Value
Options
DDR SDRAM controller debug info
Yes 1
driven to MSRCID/MDVAL (default)
Debug information is not driven on
Yes 1
ECC pins (default)
eTSEC1 and eTSEC2 Ethernet
Yes 0
interfaces operate in RGMII mode
The eTSEC1 controller operates
Yes 10
using the RGMII protocol
The eTSEC2 controller operates
Yes 10
using the RGMII protocol
The eTSEC3 controller operates
Yes 10
using the RGMII protocol
Yes 0010 PCIE1=1x, PCIE2=1x, PCI3=2x
Yes 0 eLBC ECC checking is disabled
SYSCLK is at or above 66MHz
Yes 1
(default)
Platform clock is at or above 333MHz
Yes 1
(default)
ENP1:
Yes 1
Core0 clock frequency is greater
than 1000MHz
ENP2:
0
Core0 clock frequency is less than or
equal to 1000MHz
ENP1:
Yes 1
Core1 clock frequency is greater
than 1000MHz
ENP2:
0
Core1 clock frequency is less than or
equal to 1000MHz
DDR Controller complex clock
frequency (same as DDR rate) is
Yes 1
greater than or equal to 500 MHZ
(default)
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