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Chapter 3
Input Modules
Functional Block Diagram
Receiver
Analog
Input 1A
Analog
Input 1B
Analog
Input 2A
Analog
Input 2B
Analog
Input 7A
Analog
Input 7B
Analog
Input 8A
Analog
Input 8B
Sync Inputs
+24VA
+24VB
+5VL
Input Channel 1
Signal
Presence
To FPGA
Detection
Attenuator
Buffer,
Filter,
0dBFS adjust
Single to
DC Bias
from FPGA
Diff.
Input Channel 2
•
•
•
•
Input Channel 7
Input Channel 16
AES
Sync Select
Reference
Receiver
VCXOs
Power Conversion
and
Voltage Monitoring
Thor Core
SLID
PIPE
PRTI
Figure 3-28 PM-ADCT-IB/PT-ADCT-IB Functional Block Diagram
A/D Converter 1
FPGA
In 1
Serial Data
Vcom12
AES out
Clip Detect
In 2
Clocks,
AES out
control
In 3
Serial Data
Vcom34
Clip Detect
In 4
•
AES out
•
•
A/D Converter 8
AES out
In 1
Serial Data
Vcom12
Clip Detect
In 2
Clocks,
control
In 3
Serial Data
Vcom34
Clip Detect
In 4
Clocks
I2C
Clocks
Control
Control
PRTI
AES Output 1A
AES Output 1B
•
•
•
•
•
•
AES Output 8A
AES Output 8B
TDM Output
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