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Functional Block Diagram
IN1
EQ
IN2
EQ
IN3
EQ
IN4
EQ
IN5
EQ
IN6
EQ
IN7
EQ
IN8
EQ
Figure 3-8 PM-HS-IB/PT-HS-IB Functional Block Diagram
Specifications
Specifications and designs are subject to change without notice.
Table 3-12 PM-HS-IB/PT-HS-IB Specifications
Item
Number of inputs
Input connector
Impedance
Signal type
Maximum input amplitude
Nominal input amplitude
Return loss
Equalization
OUT1A
1×2
OUT1B
OUT2A
1×2
OUT2B
OUT3A
1×2
OUT3B
OUT4A
1×2
OUT4B
OUT5A
1×2
OUT5B
OUT6A
1×2
OUT6B
OUT7A
1×2
OUT7B
OUT8A
1×2
OUT8B
270 Mb/s data rate
1.485 Gb/s data rate
Installation, Configuration, and Operation Manual
Power-up
Micro-
processor
Signal
presence
FPGA
Bypass
&
MCL
D/A
ADJ
Specification
8
75 BNC per IEC 169-8
75
SMPTE 292M SMPTE 259M, SMPTE 344M, DVB-ASI
Most other < 1Vpp digital signals, 3 Mb/s to 1.5 Gb/s
880 mV
800 mV ± 10%
> 16 dB, up to 1.5 GHz
Automatic
1,148 ft (350 m) Belden 1694A
492 ft (150 m) Belden 1694A
Platinum Frames and Modules
System control
System control
+3.3V
+24V
Power
supply
73
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