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Chapter 3
Input Modules
Composite Analog to Digital Conversion
Once the analog clamping and level processing has taken place, each channel of video is
presented to a 10-bit analog to digital converter, which is phase and frequency locked by an
internal PLL. Considering that the desired conversion is to component digital on this card,
the analog to digital converters are 2X oversampling at 27MHz (4:2:2 data rate of 13.5MHz
times 2). As a benefit of the 2X oversampling, a half-band decimation filter is applied right
after the digital conversion to reduce the data rate to 1X the pixel rate, which effectively
adds up to 3dB to the overall signal to noise ratio (SNR). Although sampled at a component
data rate, the digitized composite signal is band pass filtered into separate luminance and
chrominance channels (Y/C). The chrominance channel is sent through a quadrature
demodulator for further separation into the base component color difference channels (R -
Y / B - Y). As the color demodulation process is likely to cause artifacts in the video, the R -
Y and B - Y signals are sent through low-pass filters to reduce those artifacts and achieve
optimum bandwidth, and through a five-line adaptive comb filter to compare possible color
phase shift issues from line to line. As the next step in the color demodulation process, a
color space converter is used to convert the red and blue color components to U and V
color difference components (Cr/Cb) as needed for ITU-R 601i and SMPTE-125M type
signals.
The RGB to YUV color space conversion is defined in the following system of equations:
Y = 0.299R + 0.587G + 0.114B
U = -0.172R - 0.339G + 0.511B + 512
V = 0.511R - 0.428G - 0.083B + 512
In cases where the U/V bandwidth needs to be limited, as to prevent aliasing or
chrominance crosstalk, a set of user-adjustable notch filters is provided. Although more of
an issue in the companion encoder / digital to analog (DAC) cards, careful attention has to
be paid to the implementation of these filters as a trade-off between frequency response
and out of band noise is often encountered. In the interest of keeping the luminance or Y
signal bandwidth, a peaking filter is available to the user. There are also controls for the user
to set the brightness, contrast, sharpness, color saturation, and hue of the incoming video
signal. Once the chrominance signals have been processed, they are reunited with the
luminance (Y) channel to complete the 10-bit YUV component digital signal.
Component Digital Packaging
The parallel 10-bit component output of the ADC conversion is presented to the next
process, where it is packaged with the digitized sync information and given the proper start
of active video (SAV) and end of active video (EAV) headers for a SMPTE-125M compliant
parallel output signal. Along with the parallel 10-bit video signal, a 27 MHz clock signal is
provided for latching the data words in the downstream serializer device.
Parallel to Serial Converter
The parallel 10-bit video and clock signal are presented to the FPGA-based serializer for
conversion to SMPTE-259C serial digital component video at 270 Mb/s. The 10-bit parallel
word is latched into the serializer on the rising edge of the accompanying 27 MHz clock
signal and serialized at 10 times the data rate (270 MB/s). As the serial data is used to clock
downstream devices, the serial signal is scrambled and encoded using a non-return to zero
(NRZI) algorithm to ensure that clock transitions occur during long periods of all 1s or 0s to
keep the receiving PLLs locked.
The NRZI / scramble polynomial is defined as
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