Interrupts - Renesas M16C Series Hardware Manual

R8C/11 Group
19.2 Interrupt
19.2.1 Reading Address 00000
Do not read the address 00000
the CPU reads interrupt information (interrupt number and interrupt request level) from 00000
interrupt sequence. At this time, the acknowledged interrupt IR bit is set to "0".
If the address 00000
among the enabled interrupts is set to "0". This may cause a problem that the interrupt is canceled, or
an unexpected interrupt is generated.
19.2.2 SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to "0000
Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out
of control.
19.2.3 External Interrupt and Key Input Interrupt
Either an "L" level or an "H" level of at least 250ns width is necessary for the signal input to the INT
________
INT pins and KI
3
19.2.4 Watchdog Timer Interrupt
Reset the watchdog timer after a watchdog timer interrupt is generated.
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
16
by a program. When a maskable interrupt request is acknowledged,
16
is read by a program, the IR bit for the interrupt which has the highest priority
16
_____ _____
to KI pins regardless of the CPU clock.
0 3
page 187 of 204
19. Usage Notes
in the
16
" after reset.
16
________
to
0