Timer C - Renesas M16C Series Hardware Manual

R8C/11 Group

12.4 Timer C

Timer C is a 16-bit timer. Figure 12.28 shows a block diagram of Timer C. Figure 12.29 shows a block
diagram of CMP waveform generation unit. Figure 12.30 shows a block diagram of CMP waveform output
unit.
The Timer C has two modes: input capture mode and output compare mode.
Figures 12.31 shows TC, TM0, TM1, and TCC0 registers. Figure 12.32 shows TCC1 and TCOUT regis-
ters.
INT /TC
3 IN
TCC02 to TCC01
f
1
f
8
f
32
f
-fast
RING
TCC01 to TCC02, TCC07: Bits in TCC0 register
TCC10 to TCC12: Bits in TCC1 register
Figure 12.28 Timer C Block Diagram
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
TCC11 to TCC10
=01
2
f Sampling
1
=10
clock
2
f
8
=11
2
f
32
Other than 00
2
=00
2
f
RING128
Upper 8 bits
Capture and compare 0 register
=00
2
Upper 8 bits
=01
2
=10
2
=11
2
TCC00
Upper 8 bits
page 101 of 204
TCC07=0
Digital
Edge
filter
detection
TCC07=1
Lower 8 bits
TM0 register
Compare circuit 0
Lower 8 bits
Counter
TC register
TCC12
Compare circuit 1
Lower 8 bits
Compare register 1
TM1 register
12.4 Timer (Timer C)
INT3 interrupt
Transfer signal
Compare 0 interrupt
Timer C interrupt
TCC12
=0
=1
Timer C counter reset signal
Compare 1 interrupt