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3.1.11. 0Register BITs description (summary)
Address
CPLD
READ
n90*
WRITE
READ
n91*
WRITE
READ
n92*
WRITE
READ
n93*
WRITE
READ
n94*
WRITE
READ
n95*
WRITE
READ
n96*
WRITE
READ
n97*
BATFEN
WRITE
READ
n98*
WRITE
READ
n99*
WRITE
READ
n9A*
WRITE
READ
n9B*
WRITE
The base address for the Supervisor I/O Register, which is used for such functions as power fail
detection and the watchdog timer can be set to 190h, 290h, and 390h (see Chipset Features Setup).
D7
D6
D5
NU
PBRST
WDO
NU
NU
NU
NU
NU
_CND3
CIS3_1
CIS3_0 CBAS3_1 CBAS3_0
_CND4
CIS4_1
CIS4_0 CBAS4_1 CBAS4_0
WDEN
WDD2
WDD1
BATFLT
NU
NU
NU
D4
D3
RS485
RS232
NU
IDCHIP
WDD0
NU
RESERVED
RESERVED
RESERVED
NU
RESERVED
3.7
Installing the Board
D2
D1
D0
ST1
NU
PFO
NU
NU
_CLRHIS
WD_LOCK
NU
I2C_DATA
I2C_CLK
RESERVED
RESERV.
NU
NU
NU
WDNMI
WDNMIEN
NU
NU
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