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3.1.11 0Register BITs Description (Summary)
Address
CPLD
D7
READ
n90*
WRITE
READ
PBRST
n91*
WRITE
NU
READ
n92*
WRITE
READ
n93*
WRITE
READ
n94*
_CND3
WRITE
READ
n95*
_CND4
WRITE
READ
n96*
WDEN
WRITE
READ
n97*
BATFEN
WRITE
READ
n98*
WRITE
READ
n99*
WRITE
READ
n9A*
NU
WRITE
READ
n9B*
WRITE
The base address for the Supervisor I/O Register, which is used for such functions as power fail
detection and the watchdog timer can be set to 190h, 290h, and 390h (see Chipset Features Setup).
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D6
D5
D4
NU
RS485
RS232
WDO
NU
NU
NU
NU
IDCHIP
CIS3_1
CIS3_0 CBAS3_1 CBAS3_0
CIS4_1
CIS4_0 CBAS4_1 CBAS4_0
WDD2
WDD1
WDD0
BATFLT
NU
NU
RESERVED
RESERVED
RESERVED
NU
3-7
Installing the Board
D3
D2
D1
D0
ST1
NU
PFO
NU
NU
NU
_CLRHIS
WD_LOCK
NU
I2C_CLK
I2C_DATA
RESERVED
RESERV.
NU
NU
NU
WDNMI
WDNMIEN
NU
NU
RESERVED
NU
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