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Table 31: Summary – COM.0 REV3.0 vs REV3.1
REV3.1
REV 3.1 Description
PCIE1_CK_REF+
Second reference clock output for higher speed PCI
PCIE1_CK_REF-
Express implementation on Lanes 16 to 31
CEI_MDIO
MDIO data – for PHY setup
CEI_MDC
MDIO clock - for PHY setup
CEI_SDA
I2C data – for SFP setup, serialized status LEDs and
miscellaneous serialized signals
CEI_SCL
I2C clock for CEI I2C port
CEI_INT#
Active low interrupt input to Module from Carrier based
I2C I/O expander
ETH_PHY_INT#
Second active low interrupt input to Module from
Carrier based I2C I/O expander
CEI_RST#
Active low reset output from Module to Carrier based
I/O expander
CEI_PRSNT#
Input signal from Carrier indicating presence of CEI
compliant hardware on the Carrier
Reserved pin
Not used
Reserved pin
Not used
Reserved pins
Not used
Reserved pins
Not used
Reserved pins
Not used
Reserved pins
Not used
Reserved pin
Not used
Reserved pin
Not used
Reserved pins
Not used
www.kontron.com
COMe-bID7 User Guide Rev. 1.2
REV3.0
Reserved pins
10G_PHY_MDIO_SDA0
10G_PHY_MDC_SCL0
10G_SFP_SDA0
10G_SFP_SCL0
10G_INT0
10G_INT1
10G_PHY_RST_01
10G_PHY_CAP_01
10G_PHY_RST_23
10G_PHY_CAP_23
10G_PHY_MDIO_SDA[1:3]
10G_PHY_MDC_SCL[1:3]
10G_SFP_SDA[1:3]
10G_SFP_SCL[1:3]
10G_LED_SDA
10G_LED_SCL
10G_INT[2:3]
Pin
B29
B30
D46
C46
C39
D39
C47
D47
C35
D35
C34
D34
D45, D16, D15
C45, C16, C15
C38, C33, C32
D38, D33, D32
C36
C37
C24, D24
// 66
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