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3.5.3. J5 Signal Specification
3.5.3.1. IDE 0 Interface
Signal
/BRSTDRV
A1
/BRSTDRV
B1
PDD 0-15
B4, E3, C3, A3, D2, B2,
E1, C1, D1, A2, C2, E2,
B3, D3, A4, D4
PDREQ
A5
/PDIOW
C5
/PDIOR
E5
PIORDY
B5
/PDDACK
D5
IRQ14
E4
/IOCS16
A6
PDA 0-2
D6, C7, E6
/PCS1, /PCS3
A7, B7
PRI-PD1
D7
/PDIAG
C6
3.5.3.2. USB 0 and 1 Interfaces
Signal
Pin Assignation
USBD1-0 (+/-)
B18, C18, D19, E19
USBG 1-0
B19, D18
USBV 1-0
C19, E18
Pin Assignation
USB Data – Differential data path for USB 0 and 1 ports
USB Ground – Differential ground reference for USB 0
and 1 ports
USB Voltage – Differential power level for USB 0 and 1
ports
Description
Prim. Disk Data – These signals are used to transfer
data to or from the IDE device.
Prim. Disk DMA Request - This signal is directly driven
from the IDE device DMARQ signal. It is asserted by
the IDE device to request a data transfer.
Prim. Disk I/O Write – In normal IDE mode, this is the
command to the IDE device that it may latch data from
SDD lines.
Prim. Disk I/O Read – In normal IDE mode, this is the
command to the IDE device that it may drive data on
SDD lines.
Prim. I/O Channel Ready – In normal mode, this input
signal is driven directly by the corresponding IDE
device IORDY signal.
Prim. DMA Acknowledge – This signal directly drives
the IDE device /DMACK signal. It is asserted to
indicate to IDE DMA slave devices that a given data
transfer cycle is a DMA data transfer cycle.
IRQ14 line
IOCS16 line
Prim. Disk Address – These signals indicates which
byte in either the ATA command block or control block
is being addressed.
Description
3.35
Installing the Board
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