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cPCI-MXS64GX Technical Reference Manual
3.5.2.6. IDE 1 Interface
Signal
/BRSTDRV
A17
IDE1_ 0-15
B20, E19, C19, A19,
D18, B18, E17, C17,
D17, A18, C18, E18,
B19, D19, A20, C20
SDREQ
A21
/SDIOW
C21
/SDIOR
E21
SIORDY
B22
/SDDACK
D22
IRQ15
E22
/IOCS16
A23
SDA 0-2
D23, B23, E23
/SCS1, /SCS3
A24, B24
SEC-PD1
C24
/FAL1
E24
IDE 1 (IDE 1) is assigned to the Secondary IDE logical interface. It supports directly two
IDE devices configured as master and slave devices.
Pin Assignation
Description
Sec. Disk Data – These signals are used to transfer
data to or from the IDE device.
Sec. Disk DMA Request - This signal is directly driven
from the IDE device DMARQ signal. It is asserted by
the IDE device to request a data transfer.
Sec. Disk I/O Write – In normal IDE mode, this is the
command to the IDE device that it may latch data from
SDD lines.
Sec. Disk I/O Read – In normal IDE mode, this is the
command to the IDE device that it may drive data on
SDD lines.
Sec. I/O Channel Ready – In normal mode, this input
signal is driven directly by the corresponding IDE
device IORDY signal.
Sec. DMA Acknowledge – This signal directly drives
the IDE device /DMACK signal. It is asserted to
indicate to IDE DMA slave devices that a given data
transfer cycle is a DMA data transfer cycle.
Sec. Disk Address – These signals indicates which
byte in either the ATA command block or control block
is being addressed.
Secondary Chip Select - For ATA control register.
3.34
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