Fujitsu F2MC-8L Family series Hardware Manual page 57

Peripherals
Address: 0020 SMC1
H
Address: 0021 SRC
H
Address: 0022 SSD
H
Address: 0023 SIDR
H
Address: 0023 SODR
H
Address: 0024 SMC2
H
RDRF ORFE
0 0
0 1
1 0
1 1
HARDWARE CONFIGURATION
(c) Serial status and data register (SSD)
This register is used to indicate the current status of the UART port. When
the data communication length is 9 bits, the most significant data (bit 8) is
included.
Bit 7
RDRF
Address: 0022
H
(R)
[Bit 7] RDRF:
The RDRF flag is used to indicate the data status of the serial input data
register (SIDR).
0 Empty
1 Contains data
When the SIDR register is read after reading the SSD register with the
RDRF flag set to 1, the RDRF flag is cleared. When this flag is set to 1,
the receiver interrupt request is output.
[Bit 6] ORFE:
The ORFE flag is used to indicate that an overrun or framing error has
occurred. This flag is initialized to 0 at reset.
0 Normal
1 Error
If this flag is set, data is not transferred from the receive shift register to the
SIDR register.
When the SIDR register is read after reading the SSD register with the
ORFE flag set to 1, the ORFE flag is cleared. When this flag is set to 1,
the receiver interrupt request is output.
The status of input data is specified by the RDRF and ORFE flags as follows:
Empty
Framing error (If new data is input under this condition, RDRF is not set.)
Normal data
Overrun (previous data remains)
2– 42
Bit 6 Bit 5 Bit 4 Bit 3
ORFE TDRE TIE RIE
(R) (R) (R/W) (R/W)
(Initial value)
00100-1X
SIDR data status
Bit 2 Bit 1 Bit 0
TD8 RD8
—
/TP /RP
(R/W) (R)
B
(Initial value)
(Initial Value)