Fujitsu F2MC-8L Family series Hardware Manual page 5

Figures
Fig. 1.1 Block Diagram (MB89953) .............................................................................................1-5
Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, pitch: 0.65 mm) .......................1-6
Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, pitch: 0.8 mm) ...........................................1-7
Fig. 1.4 I/O Circuits ....................................................................................................................1-10
Fig. 2.1 Memory Space of MB89950 Series Microcontrollers .....................................................2-3
Fig. 2.2 Arrangement of 16 bit Data in Memory Space ...............................................................2-5
Fig. 2.3 Arrangement of 16 bit Data during Execution of Instruction ...........................................2-5
Fig. 2.4 Structure of Processor Status .........................................................................................2-7
Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area .......................2-7
Fig. 2.6 Register Bank Configuration ...........................................................................................2-8
Fig. 2.7 Interrupt-processing Flowchart .....................................................................................2-17
Fig. 2.8 Ports 0, 1 and 2 ............................................................................................................2-20
Fig. 2.9 Port 3 ............................................................................................................................2-22
Fig. 2.10 Port 4 ..........................................................................................................................2-24
Fig. 2.11 Timer Operation ..........................................................................................................2-28
Fig. 2.12 PWM Pulse Output .....................................................................................................2-29
Fig. 2.13 Measurement of High Pulse Width .............................................................................2-35
Fig. 2.14 Operation of Noise Clearing Circuit ............................................................................2-36
Fig. 2.15 RDRF Flag Set Timing ...............................................................................................2-46
Fig. 2.16 ORFE Flag Set Timing ...............................................................................................2-47
Fig. 2.17 TDRE Flag Set Timing ................................................................................................2-47
Fig. 2.18 Transfer Data Format (Synchronous Transfer) ..........................................................2-47
Fig. 2.19 Shift Start/Stop Timing ................................................................................................2-55
Fig. 2.20 Input/Output Shift Timing ............................................................................................2-55
Fig. 2.21 LCD Controller /Driver Block Diagram ........................................................................2-59
Fig. 2.22 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-64
Fig. 2.23 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-65
Fig. 2.24 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-66
Fig. 2.25 Connection Examples for Supply Power for Driving LCD ...........................................2-67
Fig. 2.26 Built-in Voltage Dividing resistors ...............................................................................2-68
Fig. 3.1 Clock Pulse Generator ...................................................................................................3-3
Fig. 3.2 Outline of Reset Operation .............................................................................................3-4
Fig. 3.3 Reset Vector Structure ...................................................................................................3-4
Fig. 3.4 Interrupt-processing Flowchart .......................................................................................3-6
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