Fujitsu F2MC-8L Family series Hardware Manual page 67

Peripherals
Address: 001C SMR
H
Address: 001D SDR
H
HARDWARE CONFIGURATION
[Bit 4] SOE: Serial-data output-enable bit
This bit is used to control the output pin for serial I/O.
General-purpose port pin (P44)
0
SO (serial data) output pin
1
When using P43/SI pin as SI pin, always set the DDR4 to input (bit 3 of
DDR4 = 0).
This bit is valid when the RSEL bit of the SMC2 in the UART is 1.
[Bits 3 and 2] CKS1 and CKS0: Shift-clock select bits
These bits are used to select the serial shift-clock modes.
CKS1 CKS0
0 0 Internal shift-clock mode
0 1 Internal shift-clock mode
1 0 Internal shift-clock mode
1 1 External shift-clock mode
[Bit 1] BDS: Transfer direction select bit
At serial data transfer, this bit is used to decide the transfer direction: from
the least significant bit first (LSB first) or from the most significant bit first
(MSB first).
LSB first
0
MSB first
1
Note that when this bit is rewritten after writing data to the SDR, the data
become invalid.
[Bit 0] SST: Serial I/O transfer-start bit
This bit is used to start serial I/O transfer. The bit is automatically cleared
to 0 when transfer is terminated.
Stops serial I/O transfer
0
Starts serial I/O transfer
1
Before starting transfer, ensure that transfer is stopped (SST = 0).
(b) Serial-data register (SDR)
This 8-bit register is used to hold serial I/O transfer data. (Note: Do not
write data to this register during the serial I/O operation.)
Bit 7
Address: 001D
H
(R/W)
Mode
(2 instruction cycle)
(8 instruction cycle)
(32 instruction cycle)
(SCK)
Bit 6 Bit 5 Bit 4
(R/W) (R/W) (R/W)
(Initial value)
XXXXXXXX
2– 52
(Clock rate) SCK
Output
Output
Output
Input
Bit 3 Bit 2 Bit 1 Bit 0
(R/W) (R/W) (R/W) (R/W)
B