Fujitsu F2MC-8L Family series Hardware Manual page 41

Peripherals
Address: 0012H CNTR
Address: 0013H COMR
HARDWARE CONFIGURATION
(3) Description of registers
(a) Control register (CNTR)
Bit 7 Bit 6
P/T
Address: 0012
H
(R/W)
[Bit 7] P/T: Timer/PWM operation mode switching bit
The operation is performed as the timer when bit 7 is set to 0, and as the
0 Timer
1 PWM control circuit
When switching, set channel to stop counting (TPE = 0), interrupt disabled
(TIE = 0) and interrupt request flag cleared (TIR = 0).
[Bits 5 and 4] P1 and P0: Clock-pulse select bits
Clock pulses from the prescaler or WT0 output of timer 2 (pulse-width count
timer) can be selected using P1 and P0.
P1 P0
0 0 Internal clock pulse 1 instruction cycle
0 1 Internal clock pulse 16 instruction cycles
1 0 Internal clock pulse 64 instruction cycles
1 1 Timer 2 cycle
Note that these bits must not be rewritten when the counter is operating
(TPE = 1).
[Bit 3] TPE: Counting enable bit
When these bits are set to 1, the timer or PWM control circuit starts
operation.
0 Stops counting
1 Starts counting
[Bit 2] TIR1: PWM channel interrupt request flag bit
Bit 2 goes to 1 when an interrupt source occurs. To clear the generated
interrupt source, write 0 at this bit. The meaning of bit to be read is as
follows:
2– 26
Bit 5 Bit 4 Bit 3
— P1 P0 TPE
(R/W) (R/W) (R/W)
(Initial value)
0X000000
B
Clock cycle
Bit 2 Bit 1 Bit 0
TIR OE TIE
(R/W) (R/W) (R/W)