Table of Contents
Advertisement
Peripherals
SCK
SST
IRQ
SO
SCK
SST
SIOF
SO
SCK
SST
SIOF
SO
SCK
SST
SIOF
SO
HARDWARE CONFIGURATION
(c) Interrupt functions
This module can output an interrupt request to the CPU. To output an
interrupt request, set the SIOE bit (bit 6) of the SMR to 1 to enable an
interrupt and then set the interrupt flag SIOF bit (bit 7) of the SMR after
8-bit data transfer is terminated.
#0
#1
#2
(d) Shift start/stop timing
Data transfer starts when 1 is written at the SST bit (bit 0) of the SMR, and
stops when 0 is written. When data transfer is terminated, the SST bit is
automatically cleared to 0, which stops the operation.
a. Internal shift-clock mode (LSB first)
[When transfer terminated]
#0
#1
#2
[When transfer suspended]
#0
#1
#2
b. External shift-clock mode (LSB first)
[When transfer terminated]
#0
#1
#2
2– 54
#3
#4
#5
#6
#3
#4
#5
#6
#3
#4
#5
#3
#4
#5
#6
#7
#7
#7
Advertisement
Table of Contents
